CACP4901TC Torque Magnitude R U D 1 VCD00147 Integer between 0 and 1 R U D 1 VCD00149 Integer between 0 and 22 R U D 1 VCD00150 Integer between 0 and 11 R U D 1 VCD00153 Integer between 0 and 23 R U D 1 VCD00154 Integer between 0 and 23 R U D 1 VCD00155 Integer between 0 and 23 R U D 1 VCD00156 Integer between 0 and 23 R U D 1 VCD00157 Integer between 0 and 25 R U D 1 VCD00158 Integer between 0 and 32 R U D 1 VCD00159 Integer between 0 and 45 R U D 1 VCD00160 Integer between 0 and 15 R U D 1 VCD00161 Integer between 0 and 58 R U D 1 VCD00162 Integer between 0 and 65 R U D 1 VCD00163 Integer between 0 and 7 R U D 1 VCD00164 Integer between 0 and 78 R U D 1 VCD00165 Integer between 0 and 9 R U D 1 VCD00170 Integer between 1 and 13 R U D 1 VCD00171 Integer between 1 and 2 R U D 1 VCD00173 Integer between 1 and 21 R U D 1 VCD00174 Integer between 1 and 23 R U D 1 VCD00175 Integer between 1 and 23 R U D 1 VCD00176 Integer between 1 and 25 R U D 1 VCD00177 Integer between 1 and 30 R U D 1 VCD00178 Integer between 1 and 32 R U D 1 VCD00179 Integer between 1 and 4 R U D 1 VCD00180 Integer between 1 and 40 R U D 1 VCD00181 Integer between 1 and 42 R U D 1 VCD00182 Integer between 1 and 44 R U D 1 VCD00183 Integer between 1 and 56 R U D 1 VCD00185 Integer between 1 and 57 R U D 1 VCD00186 Integer between 1 and 58 R U D 1 VCD00187 Integer between 1 and 65 R U D 1 VCD00188 Integer between 1 and 7 R U D 1 VCD00189 Integer between 0 and 61 R U D 1 VCD00190 Float between 0.1 and 16 R R D 1 VCD00194 Integer between 0 and 8 R U D 1 VCD00195 Integer between 1 and 10 R U D 1 VCD00213 Integer between 0 and 68 R U D 1 VCD00236 Integer between 0 and 20 R U D 1 VCD00237 Integer between 0 and 20 R U D 1 VCD00238 Integer between 0 and 22 R U D 1 VCD00240 Integer between 0 and 40 R U D 1 VCD00241 Integer between 0 and 51 R U D 1 VCD00243 Integer between 1 and 11 R U D 1 VCD00244 Integer between 1 and 18 R U D 1 VCD00245 Integer between 1 and 23 R U D 1 VCD00246 Integer between 1 and 23 R U D 1 VCD00247 Integer between 1 and 47 R U D 1 VCD00248 Integer between 2 and 65 R U D 1 VCD00250 Integer between 0 and 23 R U D 1 VCD00251 Integer between -1 and 3 R I D 1 VCD00254 Integer between 0 and 11 R U D 1 VCD00255 Integer between 0 and 25 R U D 1 VCD00257 Integer between 0 and 4 R U D 1 VCD00265 Integer between 0 and 25 R U D 1 VCD00266 Integer between 0 and 28 R U D 1 VCD00267 Integer between 0 and 72 R U D 1 VCD00268 Integer between 1 and 11 R U D 1 VCD00269 Integer between 1 and 25 R U D 1 VCD00270 Integer between 1 and 78 R U D 1 VCD00314 Integer between 0 and 10 R U D 1 VCD00315 Integer between 0 and 31 R U D 1 VCD00335 Integer between 0 and 36 R U D 1 VCD00336 Integer between 1 and 15 R U D 1 VCD00337 Integer between 1 and 21 R U D 1 VCD00338 Integer between 1 and 26 R U D 1 VCD00339 Integer between 1 and 6 R U D 1 VCD00340 Integer between 1 and 8 R U D 1 VCD00348 Float between -179.5 and R R D 1 VCD00349 Float between -180.0 and R R D 1 VCD00350 Float between 0.0 and 21 R R D 1 VCD00351 Integer between 193 and R U D 1 VCD00352 Integer between 1 and 16 R U D 1 VCD00353 Integer between 1 and 19 R U D 1 VCD00363 Integer between 0 and 22 R U D 1 VCD00379 Integer between 0 and 12 R U D 1 VCD00383 Integer between 0 and 16 R U D 1 VCD2X01F PCD2X01F range R U D 38 VCD2X02F PCD2X02F range R U D 10 VCD2X03F PCD2X03F range R U D 42 VCD2X04F PCD2X04F range R U D 2 VCD2X05F PCD2X05F range R U D 125 VCD2Z001 SGM Door Priority 0 To 6 R U D 1 VCDEID11 PCDEID11 range E A 20 VCDEID12 PCDEID12 range E A 5 VCDEID13 PCDEID13 range E A 12 VCDEID14 PCDEID14 range E A 2 VCDEID15 PCDEID15 range E A 58 VCDEID21 PCDEID21 range E A 20 VCDEID22 PCDEID22 range E A 5 VCDEID23 PCDEID23 range E A 14 VCDEID24 PCDEID24 range E A 2 VCDEID25 PCDEID25 range E A 58 VCDX0001 Source Sequence Count R U D 1 VCDX0002 Reserved IDs R U D 2 VCDX0003 Reserved IDs FCT R U D 1 VCDX0004 Reserved IDs MPS R U D 1 VCDX0005 INT between 200 and 255 R U D 1 VCDX0006 INT between 100 and 199 R U D 1 VCDX0007 INT equal to 0 R U D 1 VCDX0008 INT between 0 and 255 R U D 1 VCDX0009 PM RAM Memory IDs E A 2 VCDX0010 TCF_SELECT E A 4 VCDX0011 TCF1_SELECT E A 2 VCDX0012 TCF2_SELECT E A 2 VCDX0013 TCF1 and/or TCF2 E A 3 VCS2Z000 Health status R U D 1 VCTX0001 Thermal Loop Address E A 104 VIC00000 Valid Macro IDs R U D 1 VIC00005 Valid Study IDs R U D 1 VIC00010 MCP HV Range R U D 1 VIC00015 Gap HV Range R U D 1 VIC00020 MCP HV Step R U D 1 VIC00025 Gap HV Step R U D 1 VIC00030 Scan Voltage R U D 1 VIC00035 Scan LVDT R U D 1 VICCMS05 CMS Sample Window Sizes R U D 1 VID10000 Length Check/Read R U D 1 VID10001 Length Load R U D 1 VID10002 Length Load PUS R U D 1 VID10003 Voltage Step R I D 1 VID10004 Priority Events R U D 1 VID10005 Raw Events R U D 1 VID10006 UH Events R U D 1 VID10007 Integration Time R U D 1 VID10008 Coincidence R U D 1 VID10009 Energy Level R I D 1 VID10010 Iris Position R U D 1 VID10011 Iris Steps R U D 1 VID10012 CFD Level R U D 1 VID10013 Pulse Delay R U D 1 VIH6DUMP Valid length for TM65 R U D 1 B VIH6LOAD Valid length for TC62 R U D 1 B VIHDECOL Entry zero to 5 R U D 1 VIHDSROW Slot zero to 9 R U D 1 VIHFNBYT number of bytes in pkt R U D 1 B VIHMBANK MRAM bank 1 or 2 R U D 1 VIHMDUMP Valid length for Memdump R U D 1 B VIHMFILE Valid length for SMFile R U D 1 B VIHMFILL Valid length for SMFill R U D 1 B VIHMLOAD Valid length for MemLoad R U D 1 B VIHQSLOT SC slot number R U D 1 VIP06012 PHI_MEM_BootPROM_range R U H 1 VIP06013 PHI_MEM_BootPROM_size R U D 1 VIP06022 PHI_MEM_ConfigMem_range R U H 1 VIP06023 PHI_MEM_ConfigMem_size R U D 1 VIP06032 PHI_MEM_SysFPGA_range R U H 1 VIP06042 PHI_MEM_RAM_range R U H 1 VIP06043 PHI_MEM_RAM_size R U D 1 VIP06052 PHI_MEM_LEON_range R U H 1 VIP06062 PHI_MEM_Scratch_range R U H 1 VIP06063 PHI_MEM_Scratch_size R U D 1 VIP06072 PHI_MEM_Image_range R U H 1 VIP06073 PHI_MEM_Image_size R U D 1 VIP06082 PHI_MEM_RFPGA2_range R U H 1 VIP06083 PHI_MEM_RFPGA2size R U D 1 VIP06092 PHI_MEM_JUMP_range R U H 1 VIPDID00 PHI_datasetID_range R U D 1 VIPE8491 PHI_HVPS_range R I D 1 dV VIPE8522 PHI_PMP_states R U D 1 VIPE8701 PHI_ACCU_frameLen_range R U D 1 pix VIPE8702 PHI_ACCU_rows_range R U D 1 VIPE8703 PHI_ACCU_rowIter_range R U D 1 VIPE8704 PHI_ACCU_cols_range R U D 1 VIPE8705 PHI_ACCU_colIter_range R U D 1 VIPE8706 PHI_ACCU_frames_range R U D 1 VIPE95A1 PHI_NAND_slice_range R U D 1 VIPE95A2 PHI_NAND_blk0or6_range R U D 1 VIPE95A3 PHI_NAND_blk1or7_range R U D 1 VIPE95A4 PHI_NAND_blk2or8_range R U D 1 VIPE95A5 PHI_NAND_blk3or9_range R U D 1 VIPE95A6 PHI_NAND_blk4or10_range R U D 1 VIPE95A7 PHI_NAND_blk5or11_range R U D 1 VIPE95A8 PHI_NAND_page_range R U D 1 VIW00001 DPU_HK_REPORT_PER R U D 1 VIW00003 DPU_OBC_HK_REPORT_PER R U D 1 VIW00004 DPU_EVENT_REPORT_NR R U D 1 VIW00008 RPW_BLK_LEN_LOAD R U D 1 B VIW00011 RPW_BLK_LEN_DUMP R U D 1 B VIW00012 RPW_BLK_LEN_CHECK R U D 1 B VIW00018 DPU_DBS_MAX_TM_DATA_RATE R U D 1 Kbps VIW00019 DPU_SSMM_LA R U H 1 VIW00020 DPU_OBC_LA1 R U H 1 VIW00021 DPU_NOM_LA R U H 1 VIW00022 DPU_RED_LA R U H 1 VIW00023 DPU_RESET_INFO_ADDR R U H 1 VIW00024 DPU_DBS_DAS_ADDR R U H 1 VIW00025 DPU_DAS_DBS_ADDR R U H 1 VIW00026 DPU_DAS_EXE_EEPROM_ADDR1 R U H 1 VIW00027 DPU_DAS_EXE_EEPROM_ADDR2 R U H 1 VIW00028 DPU_DAS_START_ADDR R U H 1 VIW00029 DPU_RPW_EXE_RAM_ADDR R U H 1 VIW00030 DPU_SWITCH_OFF_DELAY1 R U D 1 ms VIW00031 DPU_SWITCH_OFF_DELAY2 R U D 1 ms VIW00032 DPU_SWITCH_OFF_DELAY3 R U D 1 ms VIW00033 DPU_SWITCH_OFF_DELAY4 R U D 1 ms VIW00034 DPU_SWITCH_OFF_DELAY5 R U D 1 ms VIW00035 DPU_SWITCH_OFF_DELAY6 R U D 1 ms VIW00036 DPU_SWITCH_OFF_DELAY7 R U D 1 ms VIW00037 DPU_SWITCH_OFF_DELAY8 R U D 1 ms VIW00038 DPU_SWITCH_OFF_DELAY9 R U D 1 ms VIW00039 DPU_SWITCH_OFF_DELAY10 R U D 1 ms VIW00050 DPU_PDU_LINK_ATTEMPT R U D 1 VIW00051 DPU_PDU_LINK_TIMEOUT R U D 1 ms VIW00052 DPU_PDU_FAILURE_MAX R U D 1 VIW00053 DPU_EEPROM_WRITE_ATTEMPT R U D 1 VIW00054 DPU_DMS_CONNECT_ATTEMPT R U D 1 VIW00055 DPU_DMS_CONNECT_TIMEOUT R U D 1 ms VIW00056 DPU_DMS_TX_TIMEOUT R U D 1 ms VIW00057 DPU_DMS_RX_TIMEOUT R U D 1 ms VIW00058 DPU_ADC_FAILURE_MAX R U D 1 VIW00059 DPU_DBS_HK_INIT_PER R U D 1 VIW00060 DPU_PDU_HK_INIT_PER R U D 1 VIW00061 DPU_OBC_HK_INIT_PER R U D 1 VIW00114 DPU_RMAP_TIMEOUT R U D 1 ms VIW00115 DPU_RMAP_CMD_ATTEMPT R U D 1 VIW00116 DPU_RMAP_FAILURE_MAX R U D 1 VIW00123 DPU_RPW_EXE_RAM_SIZE R U D 1 VIW00124 DPU_TRIGGER_MODE_DELAY R U D 1 s VIW00125 DPU_MODE_TIMEOUT R U D 1 ms VIW00126 DPU_DMS_S20_MISSING R U D 1 VIW00127 DPU_LFR_CMD_TIMEOUT R U D 1 ms VIW00128 DPU_TDS_CMD_TIMEOUT R U D 1 ms VIW00129 DPU_THR_CMD_TIMEOUT R U D 1 ms VIW00130 DPU_LFR_HB_MISSING R U D 1 VIW00131 DPU_TDS_HB_MISSING R U D 1 VIW00132 DPU_THR_HB_MISSING R U D 1 VIW00133 DPU_EQ_BOOT_TIMEOUT R U D 1 ms VIW00135 DPU_BIA_LINK_ATTEMPT R U D 1 VIW00136 DPU_BIA_FAILURE_MAX R U D 1 VIW00137 DPU_BIA_LINK_TIMEOUT R U D 1 ms VIW00138 DPU_ADC_READ_ATTEMPT R U D 1 VIW00139 DPU_ADC_READ_TIMEOUT R U D 1 ms VIW00140 DPU_EEPROM_FAILURE_MAX R U D 1 VIW00141 DPU_EEPROM_WRITE_TIMEOUT R U D 1 ms VIW00142 DPU_EQ_CONNECT_ATTEMPT R U D 1 VIW00143 DPU_EQ_CONNECT_TIMEOUT R U D 1 ms VIW00144 DPU_EQ_TX_TIMEOUT R U D 1 ms VIW00145 DPU_EQ_RX_TIMEOUT R U D 1 ms VIW00156 DPU_MEMORY_LOAD_ATTEMPT R U D 1 VIW00157 DPU_DAS_HK_INIT_PER R U D 1 VIW00158 DPU_DAS_STAT_HK_INIT_PER R U D 1 VIW00159 DPU_BIA_HK_INIT_PER R U D 1 VIW00160 LFR_HK_INIT_PER R U D 1 VIW00161 THR_HK_INIT_PER R U D 1 VIW00162 TDS_HK_INIT_PER R U D 1 VIW00163 DPU_S20_HK_INIT_PER R U D 1 VIW00229 LFR_HK_REPORT_PER R U D 1 VIW00235 LFR_N_SWF_L R U D 1 VIW00236 LFR_N_SWF_P R U D 1 s VIW00237 LFR_N_ASM_P R U D 1 s VIW00238 LFR_N_BP_P0 R U D 1 s VIW00239 LFR_N_BP_P1 R U D 1 s VIW00241 LFR_B_BP_P0 R U D 1 s VIW00242 LFR_B_BP_P1 R U D 1 s VIW00244 LFR_S1_BP_P1 R U D 1 s VIW00245 LFR_S2_BP_P0 R U D 1 s VIW00246 LFR_S2_BP_P1 R U D 1 s VIW00251 TDS_N_SNAPSHOTS_NR R U D 1 VIW00254 TDS_S2_SNAPSHOTS_NR R U D 1 VIW00343 TDS_N_QUEUE_LEN R U D 1 VIW00344 TDS_N_STAT_DATA_PERIOD R U D 1 s VIW00345 TDS_N_1D_HIST_PERIOD R U D 1 s VIW00346 TDS_N_2D_HIST_PERIOD R U D 1 s VIW00404 TDS_S2_QUEUE_LEN R U D 1 VIW00449 TDS_LFM_WFS_DELAY R U D 1 s VIW00452 TDS_LFM_SPEC_FREQ_AXIS R U D 1 VIW00459 TDS_HK_REPORT_PER R U D 1 VIW00460 THR_N_CNT_TS R U D 1 VIW00469 THR_N_CNT_IS R U D 1 VIW00472 THR_N_CNT_HS R U D 1 VIW00478 THR_N_CNT_HSS R U D 1 VIW00483 THR_N_CNT_DO_AN R U D 1 VIW00492 THR_B_CNT_TS R U D 1 VIW00500 THR_B_CNT_IS R U D 1 VIW00503 THR_B_CNT_HS R U D 1 VIW00509 THR_B_CNT_HSS R U D 1 VIW00514 THR_B_CNT_DO_AN R U D 1 VIW00523 THR_CA_CNT_TS R U D 1 VIW00531 THR_CA_CNT_IS R U D 1 VIW00534 THR_CA_CNT_HS R U D 1 VIW00540 THR_CA_CNT_HSS R U D 1 VIW00545 THR_CA_CNT_DO_AN R U D 1 VIW00554 THR_HK_REPORT_PER R U D 1 VIW00935 DPU_TIME_DISPATCH_DELAY R U D 1 ms VIW00936 RPW_DELAY_WITHOUT_CTR R U D 1 s VIW00937 DPU_TIME_FAILURE_MAX R U D 1 VIW00945 DPU_BIAS_P5V_WDEV R U D 1 VIW00946 DPU_BIAS_P5V_FDEV R U D 1 VIW00950 DPU_BIAS_M5V_WDEV R U D 1 VIW00951 DPU_BIAS_M5V_FDEV R U D 1 VIW00955 DPU_BIAS_3V3_WDEV R U D 1 VIW00956 DPU_BIAS_3V3_FDEV R U D 1 VIW00960 DPU_BIAS_1V5_WDEV R U D 1 VIW00961 DPU_BIAS_1V5_FDEV R U D 1 VIW00965 DPU_LFR_P5V_WDEV R U D 1 VIW00966 DPU_LFR_P5V_FDEV R U D 1 VIW00970 DPU_LFR_M5V_WDEV R U D 1 VIW00971 DPU_LFR_M5V_FDEV R U D 1 VIW00975 DPU_LFR_3V3_WDEV R U D 1 VIW00976 DPU_LFR_3V3_FDEV R U D 1 VIW00980 DPU_LFR_1V5_WDEV R U D 1 VIW00981 DPU_LFR_1V5_FDEV R U D 1 VIW00985 DPU_TDS_P5V_WDEV R U D 1 VIW00986 DPU_TDS_P5V_FDEV R U D 1 VIW00990 DPU_TDS_M5V_WDEV R U D 1 VIW00991 DPU_TDS_M5V_FDEV R U D 1 VIW00995 DPU_TDS_3V3_WDEV R U D 1 VIW00996 DPU_TDS_3V3_FDEV R U D 1 VIW01000 DPU_TDS_1V5_WDEV R U D 1 VIW01001 DPU_TDS_1V5_FDEV R U D 1 VIW01005 DPU_THR_P12V_WDEV R U D 1 VIW01006 DPU_THR_P12V_FDEV R U D 1 VIW01010 DPU_THR_P5V_WDEV R U D 1 VIW01011 DPU_THR_P5V_FDEV R U D 1 VIW01015 DPU_THR_M5V_WDEV R U D 1 VIW01016 DPU_THR_M5V_FDEV R U D 1 VIW01020 DPU_THR_3V3_WDEV R U D 1 VIW01021 DPU_THR_3V3_FDEV R U D 1 VIW01025 DPU_THR_1V5_WDEV R U D 1 VIW01026 DPU_THR_1V5_FDEV R U D 1 VIW01030 DPU_ANT1_P5V_WDEV R U D 1 VIW01031 DPU_ANT1_P5V_FDEV R U D 1 VIW01035 DPU_ANT1_M5V_WDEV R U D 1 VIW01036 DPU_ANT1_M5V_FDEV R U D 1 VIW01040 DPU_ANT2_P5V_WDEV R U D 1 VIW01041 DPU_ANT2_P5V_FDEV R U D 1 VIW01045 DPU_ANT2_M5V_WDEV R U D 1 VIW01046 DPU_ANT2_M5V_FDEV R U D 1 VIW01050 DPU_ANT3_P5V_WDEV R U D 1 VIW01051 DPU_ANT3_P5V_FDEV R U D 1 VIW01055 DPU_ANT3_M5V_WDEV R U D 1 VIW01056 DPU_ANT3_M5V_FDEV R U D 1 VIW01060 DPU_SCM_P12V_WDEV R U D 1 VIW01061 DPU_SCM_P12V_FDEV R U D 1 VIW01065 DPU_SCM_M5V_WDEV R U D 1 VIW01066 DPU_SCM_M5V_FDEV R U D 1 VIW01118 DPU_N_CWF_F3_CHANNEL_NR R U D 1 VIW01119 DPU_N_CWF_F3_DATA_POS R U D 1 VIW01120 DPU_N_CWF_F3_SAMPLE_POS R U D 1 VIW01121 DPU_N_CWFL_F3_CHANNEL_NR R U D 1 VIW01122 DPU_N_CWFL_F3_DATA_POS R U D 1 VIW01123 DPU_N_CWFL_F3_SAMPLE_POS R U D 1 VIW01124 DPU_B_CWF_F2_CHANNEL_NR R U D 1 VIW01125 DPU_B_CWF_F2_DATA_POS R U D 1 VIW01126 DPU_B_CWF_F2_SAMPLE_POS R U D 1 VIW01127 DPU_N_SWF_F0_CHANNEL_NR R U D 1 VIW01128 DPU_N_SWF_F0_DATA_POS R U D 1 VIW01129 DPU_N_SWF_F0_SAMPLE_POS R U D 1 VIW01130 DPU_N_SWF_F1_CHANNEL_NR R U D 1 VIW01131 DPU_N_SWF_F1_DATA_POS R U D 1 VIW01132 DPU_N_SWF_F1_SAMPLE_POS R U D 1 VIW01133 DPU_N_SWF_F2_CHANNEL_NR R U D 1 VIW01134 DPU_N_SWF_F2_DATA_POS R U D 1 VIW01135 DPU_N_SWF_F2_SAMPLE_POS R U D 1 VIW01136 DPU_S1_CWF_F1_CHANNEL_NR R U D 1 VIW01137 DPU_S1_CWF_F1_DATA_POS R U D 1 VIW01138 DPU_S1_CWF_F1_SAMPLE_POS R U D 1 VIW01139 DPU_S2_CWF_F2_CHANNEL_NR R U D 1 VIW01140 DPU_S2_CWF_F2_DATA_POS R U D 1 VIW01141 DPU_S2_CWF_F2_SAMPLE_POS R U D 1 VIW01142 DPU_N_RSWF_CHANNEL_POS R U D 1 VIW01143 DPU_N_RSWF_DATA_POS R U D 1 VIW01144 DPU_N_RSWF_SAMPLE_POS R U D 1 VIW01145 DPU_N_TSWF_CHANNEL_POS R U D 1 VIW01146 DPU_N_TSWF_DATA_POS R U D 1 VIW01147 DPU_N_TSWF_SAMPLE_POS R U D 1 VIW01148 DPU_S1_RSWF_CHANNEL_POS R U D 1 VIW01149 DPU_S1_RSWF_DATA_POS R U D 1 VIW01150 DPU_S1_RSWF_SAMPLE_POS R U D 1 VIW01151 DPU_S2_TSWF_CHANNEL_POS R U D 1 VIW01152 DPU_S2_TSWF_DATA_POS R U D 1 VIW01153 DPU_S2_TSWF_SAMPLE_POS R U D 1 VIW01154 DPU_LFM_RSWF_CHANNEL_POS R U D 1 VIW01155 DPU_LFM_RSWF_DATA_POS R U D 1 VIW01156 DPU_LFM_RSWF_SAMPLE_POS R U D 1 VIW01157 DPU_LFM_CWF_CHANNEL_POS R U D 1 VIW01158 DPU_LFM_CWF_DATA_POS R U D 1 VIW01159 DPU_LFM_CWF_SAMPLE_POS R U D 1 VIW01160 DPU_SID_POSITION R U D 1 VIW01161 DPU_PACKET_LEN_POS R U D 1 VIW01170 DPU_DMS_S20_TIMEOUT R U D 1 VIW01171 DPU_LFR_HB_TIMEOUT R U D 1 VIW01172 DPU_TDS_HB_TIMEOUT R U D 1 VIW01173 DPU_THR_HB_TIMEOUT R U D 1 VIW01204 DPU_IIT_HK_INIT_PER R U D 1 VIW01215 DPU_DAS_PWR_WARN_CNT R U D 1 VIW01216 DPU_DAS_PWR_FAIL_CNT R U D 1 VIW01242 DPU_DAS_TEMP_FAIL_CNT R U D 1 VIW01282 DPU_DAS_BHV_FAIL_CNT R U D 1 VIW01298 DPU_BIA_SWEEP_STEP_NR R U D 1 VIW01302 LFR_KCOEFF_FREQUENCY R U D 1 VIW01349 DPU_DAS_PWR_WARN_MAX R U D 1 VIW01350 DPU_DAS_PWR_FAIL_MAX R U D 1 VIW01351 DPU_DAS_PWR_WARN_PER R U D 1 s VIW01352 DPU_DAS_PWR_FAIL_PER R U D 1 s VIW01353 DPU_TDS_SBM2_TSWF_PER R U D 1 s VIW01354 DPU_TDS_S2_SNAPSHOTS_NR R U D 1 VIW01355 DPU_TDS_S2_QUALITY R U D 1 VIW01358 DPU_BIA_SWEEP_FIRST_IDX R U D 1 VIW01379 TDS_DIAGNOSIS_ASI R U D 1 VIW01383 TDS_LFM_PS_SM_RATIO R U D 1 VIW01386 DPU_N_MAMP_CHANNEL_POS R U D 1 VIW01387 DPU_N_MAMP_DATA_POS R U D 1 VIW01388 DPU_N_MAMP_SAMPLE_POS R U D 1 VIW01394 DPU_EQ_FAILURE_MAX R U D 1 VIW01395 DPU_EQ_FAILURE_DELAY R U D 1 s VIW01396 DPU_EQ_SWITCH_ON_ATTEMPT R U D 1 VIW01402 THR_N_TS_SEQ_POS R U D 1 VIW01403 THR_N_IS_SEQ_POS R U D 1 VIW01404 THR_N_HS_SEQ_POS R U D 1 VIW01405 THR_N_HSS_SEQ_POS R U D 1 VIW01406 THR_N_DO_AN_SEQ_POS R U D 1 VIW01407 THR_B_TS_SEQ_POS R U D 1 VIW01408 THR_B_IS_SEQ_POS R U D 1 VIW01409 THR_B_HS_SEQ_POS R U D 1 VIW01410 THR_B_HSS_SEQ_POS R U D 1 VIW01411 THR_B_DO_AN_SEQ_POS R U D 1 VIW01412 THR_CA_TS_SEQ_POS R U D 1 VIW01413 THR_CA_IS_SEQ_POS R U D 1 VIW01414 THR_CA_HS_SEQ_POS R U D 1 VIW01415 THR_CA_HSS_SEQ_POS R U D 1 VIW01416 THR_CA_DO_AN_SEQ_POS R U D 1 VIW01482 DPU_S20_HK_REPORT_PER R U D 1 VIW01486 DPU_SBM1_Q_OFFSET R R D 1 VIW01487 DPU_SBM1_Q_LSB R R D 1 VIW01488 DPU_SBM1_DT1_SBM1 R U D 1 s VIW01489 DPU_SBM1_DT2_SBM1 R U D 1 s VIW01490 DPU_SBM1_DT3_SBM1 R U D 1 s VIW01491 DPU_SBM1_ALPHA R R D 1 VIW01492 DPU_SBM1_BETA R R D 1 VIW01493 DPU_SBM1_GAMMA R R D 1 VIW01494 DPU_SBM1_ALPHA2 R R D 1 VIW01495 DPU_SBM1_BETA2 R R D 1 VIW01496 DPU_SBM1_QM R R D 1 VIW01497 DPU_SBM1_DELTA_BM R R D 1 VIW01498 DPU_SBM1_DELTA_NPM R R D 1 VIW01499 DPU_SBM1_DELTA_VM R R D 1 VIW01500 DPU_SBM1_CR R R D 1 VIW01501 DPU_SBM1_DELTA_VM2 R R D 1 VIW01502 DPU_SBM1_A0 R R D 1 VIW01503 DPU_SBM1_A1 R R D 1 V VIW01504 DPU_SBM1_A2 R R D 1 VIW01505 DPU_SBM1_A3 R R D 1 V VIW01506 DPU_SBM1_A4 R R D 1 VIW01507 DPU_SBM1_A5 R R D 1 V VIW01508 DPU_SBM1_B_LSB R R D 1 nT VIW01509 DPU_SBM1_PB_1 R R D 1 #/nT VIW01510 DPU_SBM1_PB_2 R R D 1 #/nT VIW01511 DPU_SBM1_PB_3 R R D 1 #/nT VIW01512 DPU_SBM1_PB_4 R R D 1 #/nT VIW01513 DPU_SBM1_PB_5 R R D 1 #/nT VIW01514 DPU_SBM1_PB_6 R R D 1 #/nT VIW01515 DPU_SBM1_PB_7 R R D 1 #/nT VIW01516 DPU_SBM1_PB_8 R R D 1 #/nT VIW01517 DPU_SBM1_PB_9 R R D 1 #/nT VIW01518 DPU_SBM1_PB_10 R R D 1 #/nT VIW01519 DPU_SBM1_PB_11 R R D 1 #/nT VIW01520 DPU_SBM1_PB_12 R R D 1 #/nT VIW01523 DPU_SBM1_NP_OFFSET R R D 1 VIW01524 DPU_SBM1_NP_LSB R R D 1 #/cc VIW01525 DPU_SBM1_S20_CYCLE R U D 1 VIW01527 DPU_SBM2_RUAS R R D 1 VIW01528 DPU_SBM2_DT2 R U D 1 s VIW01529 DPU_SBM2_DT_EPD R U D 1 s VIW01532 DPU_SBM2_DT_LW R U D 1 s VIW01533 DPU_SBM2_DT_LW_F R U D 1 s VIW01534 DPU_SBM2_DT_SBM2 R U D 1 s VIW01535 DPU_SBM2_DT_SBM2_F R U D 1 s VIW01536 DPU_SBM2_EPEAK_THRES R U D 1 VIW01537 DPU_SBM2_EPEAK_THRES_F R U D 1 VIW01538 DPU_SBM2_FP_MAX R R D 1 Hz VIW01539 DPU_SBM2_FP_MIN R R D 1 Hz VIW01540 DPU_SBM2_N_LW_THRES R R D 1 VIW01541 DPU_SBM2_NW_THRES R R D 1 VIW01542 DPU_SBM2_NW_THRES_F R R D 1 VIW01544 DPU_SBM2_Q_OFFSET R R D 1 VIW01545 DPU_SBM2_Q_LSB R R D 1 VIW01547 DPU_VSC_C1 R R D 1 VIW01548 DPU_VSC_C2 R R D 1 VIW01549 DPU_VSC_C3 R R D 1 VIW01550 DPU_VSC_ALPHA R R D 1 VIW01551 DPU_VSC_BETA R R D 1 VIW01555 DPU_SC_V_F3_OFFSET R R D 1 VIW01556 DPU_SC_V_F3_LSB R R D 1 V VIW01557 DPU_SC_E1_F3_OFFSET R R D 1 VIW01558 DPU_SC_E1_F3_LSB R R D 1 V VIW01559 DPU_SC_E2_F3_OFFSET R R D 1 VIW01560 DPU_SC_E2_F3_LSB R R D 1 V VIW01581 RPW_SPARE8_1 R U D 1 VIW01582 RPW_SPARE8_2 R U D 1 VIW01583 RPW_SPARE8_3 R U D 1 VIW01589 DPU_SBM1_VX_OFFSET R R D 1 VIW01590 DPU_SBM1_VY_OFFSET R R D 1 VIW01591 DPU_SBM1_VZ_OFFSET R R D 1 VIW01592 DPU_SBM1_VX_LSB R R D 1 km/s VIW01593 DPU_SBM1_VY_LSB R R D 1 km/s VIW01594 DPU_SBM1_VZ_LSB R R D 1 km/s VIW01595 DPU_SBM2_N_LW_THRES_F R R D 1 VIW01596 DPU_V_SC_OFFSET R R D 1 V VIW01597 DPU_V_SC_LSB R R D 1 V VIW01654 DPU_SBM2_DELTA_F_THRES1 R R D 1 VIW01655 DPU_SBM2_DELTA_F_THRES2 R R D 1 VIW01656 DPU_SBM2_NEPD_THRES1 R R D 1 VIW01657 DPU_SBM2_NEPD_THRES2 R R D 1 VIW01658 DPU_SCRUBBING_PERIOD R U D 1 s VIW01672 THR_N_SET_HLS1_NR_FREQ R U D 1 VIW01673 THR_N_SET_HLS2_NR_FREQ R U D 1 VIW01674 THR_B_SET_HLS1_NR_FREQ R U D 1 VIW01675 THR_B_SET_HLS2_NR_FREQ R U D 1 VIW01695 LFR_PAS_FILTER_MODULUS R U D 1 s VIW01696 LFR_PAS_FILTER_TBAD R R D 1 s VIW01697 LFR_PAS_FILTER_OFFSET R U D 1 s VIW01698 LFR_PAS_FILTER_SHIFT R R D 1 s VIW01716 DPU_DAS_RW1_K1 R R D 1 VIW01717 DPU_DAS_RW1_K2 R R D 1 VIW01718 DPU_DAS_RW1_K3 R R D 1 VIW01719 DPU_DAS_RW1_K4 R R D 1 VIW01720 DPU_DAS_RW2_K1 R R D 1 VIW01721 DPU_DAS_RW2_K2 R R D 1 VIW01722 DPU_DAS_RW2_K3 R R D 1 VIW01723 DPU_DAS_RW2_K4 R R D 1 VIW01724 DPU_DAS_RW3_K1 R R D 1 VIW01725 DPU_DAS_RW3_K2 R R D 1 VIW01726 DPU_DAS_RW3_K3 R R D 1 VIW01727 DPU_DAS_RW3_K4 R R D 1 VIW01728 DPU_DAS_RW4_K1 R R D 1 VIW01729 DPU_DAS_RW4_K2 R R D 1 VIW01730 DPU_DAS_RW4_K3 R R D 1 VIW01731 DPU_DAS_RW4_K4 R R D 1 VNISLP01 Link Priority R U D VSM00002 Collection Interval R U D 1 VSM00005 FDU Block ID range R U D 1 VSM00006 FTST Data Vol range R U D 1 VSM00009 DR RN for 15 145 R U D 1 VSM00010 Sto RN PS id TC 15 1 2 R U D 1 VSM00011 PS id range R U D 1 VSM00012 Number of APID R U D 1 VSM00013 Number of PS ID R U D 1 VSM00018 PS Default downlink prio R U D 1 VSM00022 Direct tc data Lenght R U D 1 VSM00024 Partition to be tested R U D 1 VSM00025 Stored file size R U D 1 VSM00026 Target logical address R U D 1 VST03002 Range Definition R U D 1 VST05001 Range Definition R U D 1 VST05002 Range Definition R U D 1 VST05003 Range Definition R U D 1 VST05004 Range Definition R U D 1 VST05023 Range Definition R U D 1 VST05027 Range Definition R U D 1 VST05028 Range Definition R U D 1 VST05029 Range Definition R U D 1 VST05030 Range Definition R U D 1 VST05052 Range Definition R U D 1 VST05053 Range Definition R U D 1 VST05055 Range Definition R U D 1 VST06002 Range Definition R U D 1 VST06003 Range Definition R U D 1 VST06005 Range Definition R U D 1 VST06006 Range Definition R U D 1 VST06007 Range Definition R U D 1 VST06008 Range Definition R U D 1